Invention Grant
- Patent Title: Method for preventing excessive etching of edges of an insulator layer
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Application No.: US15679937Application Date: 2017-08-17
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Publication No.: US10249508B2Publication Date: 2019-04-02
- Inventor: Xianchao Wang
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Applicant Address: CN Beijing CN Shanghai
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee Address: CN Beijing CN Shanghai
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN201610803758 20160906
- Main IPC: H01L29/16
- IPC: H01L29/16 ; H01L21/311 ; H01L21/3213 ; B81C1/00 ; H01L21/02

Abstract:
A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.
Public/Granted literature
- US20180068864A1 METHOD FOR PREVENTING EXCESSIVE ETCHING OF EDGES OF AN INSULATOR LAYER Public/Granted day:2018-03-08
Information query
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