Invention Grant
- Patent Title: Method for manufacturing a semiconductor device comprising a thin semiconductor wafer
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Application No.: US15459099Application Date: 2017-03-15
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Publication No.: US10249499B2Publication Date: 2019-04-02
- Inventor: Wolfgang Janisch , Atze de Vries , Sven Matthias
- Applicant: ABB SCHWEIZ AG
- Applicant Address: CH Baden
- Assignee: ABB Schweiz AG
- Current Assignee: ABB Schweiz AG
- Current Assignee Address: CH Baden
- Agency: Taft Stettinius & Hollister LLP
- Agent J. Bruce Schelkopf
- Priority: EP14184793 20140915
- Main IPC: H01L21/22
- IPC: H01L21/22 ; H01L21/225 ; H01L21/20 ; H01L29/66 ; H01L29/739 ; H01L21/762 ; H01L29/744 ; H01L21/283 ; H01L21/673 ; H01L29/08

Abstract:
A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.
Public/Granted literature
- US20180151367A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A THIN SEMICONDUCTOR WAFER Public/Granted day:2018-05-31
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