Invention Grant
- Patent Title: Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof
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Application No.: US15356277Application Date: 2016-11-18
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Publication No.: US10249366B2Publication Date: 2019-04-02
- Inventor: Makoto Kitagawa , Tomohito Tsushima , Wataru Otsuka , Takafumi Kunihiro
- Applicant: Sony Semiconductor Solutions Corporation
- Applicant Address: JP Kanagawa
- Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sheridan Ross P.C.
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C7/04

Abstract:
An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.
Public/Granted literature
- US20180366188A9 INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2018-12-20
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