Invention Grant
- Patent Title: Methods and apparatuses for calculating FP (full precision) and PP (partial precision) values
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Application No.: US15685312Application Date: 2017-08-24
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Publication No.: US10248417B2Publication Date: 2019-04-02
- Inventor: Huaisheng Zhang , Dacheng Liang , Boming Chen , Renyu Bian
- Applicant: VIA Alliance Semiconductor Co., Ltd.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agency: McClure, Qualey & Rodack, LLP
- Priority: CN201710499092 20170627
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F7/485 ; G06F7/487 ; G06F7/53 ; G06F7/499

Abstract:
A method for calculating FP (Full Precision) and PP (Partial Precision) values, performed by an ID (Instruction Decode) unit, contains at least the following steps: decoding an instruction request from a compiler; executing a loop m times to generate m microinstructions for calculating first-type data, or n times to generate n microinstructions for calculating second-type data according to the instruction mode of the instruction request, thereby enabling ALGs (Arithmetic Logic Groups) to execute lanes of a thread. m is less than n and the precision of the first-type data is lower than the precision of the second-type data.
Public/Granted literature
- US20180373535A1 METHODS AND APPARATUSES FOR CALCULATING FP (FULL PRECISION) AND PP (PARTIAL PRECISION) VALUES Public/Granted day:2018-12-27
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