Invention Grant
- Patent Title: System, method and test layout for detecting leakage current
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Application No.: US15260361Application Date: 2016-09-09
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Publication No.: US10247766B2Publication Date: 2019-04-02
- Inventor: Fei Luo
- Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Applicant Address: CN Shanghai
- Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Current Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Current Assignee Address: CN Shanghai
- Agency: Tianchen LLC
- Priority: CN201510592962 20150917
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/26 ; H01L21/66 ; G01R31/30

Abstract:
A test layout, a system, and a method for detecting leakage current are disclosed. The test layout module includes M PN junction diode leakage current test units formed in the FEOL process, parallel-connect with a classical leakage current test unit formed in the metal layer; wherein, P-regions of the PN junction diodes are connected to a high potential, N-regions of the PN junction diodes are connected to a low potential, the junction areas of the PN junction diodes are different each other, each of the PN junction diode leakage current test units is controlled by one switch respectively, the positive integer M is greater than or equal to 1. Through paralleling the PN junction diodes formed in the FEOL process with the classical leakage current test unit in the metal layer, not only the required test layout area utilized to detect the leakage current in the metal layer is reduced, but also the detecting accuracy is further enhanced.
Public/Granted literature
- US20170082673A1 SYSTEM, METHOD AND TEST LAYOUT FOR DETECTING LEAKAGE CURRENT Public/Granted day:2017-03-23
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