Invention Grant
- Patent Title: Selective deposition utilizing sacrificial blocking layers for semiconductor devices
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Application No.: US15527288Application Date: 2014-12-19
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Publication No.: US10243080B2Publication Date: 2019-03-26
- Inventor: Grant Kloster , Scott B. Clendenning , Rami Hourani , Szuya S. Liao , Patricio E. Romero , Florian Gstrein
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2014/071717 WO 20141219
- International Announcement: WO2016/099570 WO 20160623
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/51 ; H01L29/423 ; H01L21/28 ; H01L21/3105 ; H01L21/311 ; H01L21/02 ; H01L29/06 ; H01L29/786 ; H01L21/32 ; H01L23/498

Abstract:
Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
Public/Granted literature
- US20170330972A1 SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES Public/Granted day:2017-11-16
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