Invention Grant
- Patent Title: Thin film transistor and display panel
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Application No.: US15327588Application Date: 2015-03-27
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Publication No.: US10243003B2Publication Date: 2019-03-26
- Inventor: Nobutake Nodera , Shigeru Ishida , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
- Applicant: Sakai Display Products Corporation
- Applicant Address: JP Sakai-shi, Osaka
- Assignee: Sakai Display Products Corporation
- Current Assignee: Sakai Display Products Corporation
- Current Assignee Address: JP Sakai-shi, Osaka
- Agency: Bozicevic, Field & Francis LLP
- Agent Rudy J. Ng; Bret E. Field
- International Application: PCT/JP2015/059702 WO 20150327
- International Announcement: WO2016/157313 WO 20161006
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/786 ; H01L29/66

Abstract:
The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.
Public/Granted literature
- US20170154901A1 Thin Film Transistor and Display Panel Public/Granted day:2017-06-01
Information query
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