Invention Grant
- Patent Title: Shielded vertically stacked data line architecture for memory
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Application No.: US15676659Application Date: 2017-08-14
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Publication No.: US10242746B2Publication Date: 2019-03-26
- Inventor: Koji Sakui
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/24 ; G11C16/34 ; G11C7/12 ; G11C16/10 ; G11C7/18

Abstract:
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can he configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.
Public/Granted literature
- US20180122482A1 SHIELDED VERTICALLY STACKED DATA LINE ARCHITECTURE FOR MEMORY Public/Granted day:2018-05-03
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