Invention Grant
- Patent Title: Semiconductor device and manufacturing method therefor
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Application No.: US15298958Application Date: 2016-10-20
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Publication No.: US10229989B2Publication Date: 2019-03-12
- Inventor: Hitoshi Matsuura
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Koutou-ku, Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Koutou-ku, Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2015-207889 20151022
- Main IPC: H01L29/739
- IPC: H01L29/739 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L29/66 ; H01L29/10

Abstract:
A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n−-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n−-type drift region is used as the reverse transfer capacitance.
Public/Granted literature
- US10304949B2 Semiconductor device and manufacturing method therefor Public/Granted day:2019-05-28
Information query
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