Invention Grant
- Patent Title: Semiconductor chip and multi-chip package using thereof
-
Application No.: US15189437Application Date: 2016-06-22
-
Publication No.: US10229877B2Publication Date: 2019-03-12
- Inventor: Po Chun Lin
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW Taoyuan
- Assignee: Nanya Technology Corporation
- Current Assignee: Nanya Technology Corporation
- Current Assignee Address: TW Taoyuan
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L23/522 ; H01L21/768 ; H01L23/528 ; H01L23/544 ; H01L25/11 ; H01L25/00 ; H01L25/065

Abstract:
The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.
Public/Granted literature
- US20170373003A1 SEMICONDUCTOR CHIP AND MULTI-CHIP PACKAGE USING THEREOF Public/Granted day:2017-12-28
Information query
IPC分类: