A timing controller including a memory unit configured to store image data with respect to p*q sub-pixels defined using p numbers of data lines and q numbers of gate lines, a reception unit configured to receive, from a host, (n+m)-bit image data with respect to each of two or more of the sub-pixels, a controller configured to generate pseudo control data corresponding to m-bit image data of the two or more of the sub-pixels, and an output unit configured to output n-bit image data with respect to each of the sub-pixels to a digital unit of a data driving unit, and output the pseudo control data to an analog unit of the data driving unit.