Invention Grant
- Patent Title: Techniques for escalating interrupts in a processing unit using virtual processor thread groups and software stack levels
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Application No.: US15824545Application Date: 2017-11-28
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Publication No.: US10229075B2Publication Date: 2019-03-12
- Inventor: Richard L. Arndt , Florian A. Auernhammer
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Michael R. Long; Steven L. Bennett
- Main IPC: G06F13/26
- IPC: G06F13/26 ; G06F12/122 ; G06F13/40 ; G06F13/24 ; G06F13/28 ; G06F9/54 ; G06F12/12

Abstract:
A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.
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