Wafer scale thermoelectric energy harvester having interleaved, opposing thermoelectric legs and manufacturing techniques therefor
Abstract:
An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate. In other embodiments, one or more substrates may have trenches formed therein to capture eutectic material that facilitates bonds between components from each of the substrates and prevent inadvertent short circuits that may occur between components of the circuit system.
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