Invention Grant
- Patent Title: Instruction and logic to expose error domain topology to facilitate failure isolation in a processor
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Application No.: US15372734Application Date: 2016-12-08
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Publication No.: US10223187B2Publication Date: 2019-03-05
- Inventor: Ashok Raj , Narayan Ranganathan , Mohan J. Kumar , Vincent J. Zimmer
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F11/07

Abstract:
A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.
Public/Granted literature
- US20180165144A1 INSTRUCTION AND LOGIC TO EXPOSE ERROR DOMAIN TOPOLOGY TO FACILITATE FAILURE ISOLATION IN A PROCESSOR Public/Granted day:2018-06-14
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