Invention Grant
- Patent Title: Semiconductor device with relaxation reduction liner and associated methods
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Application No.: US14048232Application Date: 2013-10-08
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Publication No.: US10204982B2Publication Date: 2019-02-12
- Inventor: Pierre Morin , Qing Liu , Nicolas Loubet
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/84 ; H01L27/12 ; H01L29/78 ; H01L21/8238

Abstract:
A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.
Public/Granted literature
- US20150097212A1 SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS Public/Granted day:2015-04-09
Information query
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