An integrated circuit chip with reverse engineering prevention includes: a signal generator part configured to generate a first signal; a metal line part configured to receive the first signal generated at the signal generator part and generate a second signal; a comparison logic part configured to compare the first signal generated at the signal generator part and the second signal generated at the metal line part; and a signal routing part formed on both sides of the metal line part to connect the signal generator part with the metal line part at one side and connect the metal line part with the comparison logic part at the other side, where the signal routing part is a shift register.