Invention Grant
- Patent Title: Mechanism to provide back-to-back testing of memory controller operation
-
Application No.: US15442039Application Date: 2017-02-24
-
Publication No.: US10204025B2Publication Date: 2019-02-12
- Inventor: Lakshminarayana Pappu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/277 ; G06F13/42 ; G06F13/38 ; G06F13/40 ; G11C29/32 ; G11C29/38 ; G06F11/22 ; G11C29/12

Abstract:
Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.
Public/Granted literature
- US20180246796A1 MECHANISM TO PROVIDE BACK-TO-BACK TESTING OF MEMORY CONTROLLER OPERATION Public/Granted day:2018-08-30
Information query