Invention Grant
- Patent Title: Method for implementing memristive logic gates
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Application No.: US15603370Application Date: 2017-05-23
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Publication No.: US10199103B2Publication Date: 2019-02-05
- Inventor: Anubhav Jayraj Jagtap
- Applicant: Anubhav Jayraj Jagtap
- Agency: MU P.C.
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H03K19/20 ; H01L45/00

Abstract:
An embodiment of the present invention provides a method for implementing Boolean functionality to create AND, OR, NAND, NOR, or NOT logic gates using a single memristor. In an embodiment, a first voltage is applied to the memristor within a predetermined range of one of the prescribed Boolean functions to be performed by the memristor. A second voltage is then applied within the predetermined range of the prescribed Boolean function. The memristor then provides an output based on the Boolean function that has been prescribed. In an embodiment, the resistance value of the memristor is then reset by a reset pulse, wherein the reset pulse is another applied voltage.
Public/Granted literature
- US20170337968A1 Method for Implementing Memristive Logic Gates Public/Granted day:2017-11-23
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