- Patent Title: Memory controller, memory system, and information processing system
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Application No.: US15736058Application Date: 2016-04-27
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Publication No.: US10199102B2Publication Date: 2019-02-05
- Inventor: Haruhiko Terada
- Applicant: Sony Corporation
- Applicant Address: JP Tokyo
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP Tokyo
- Agency: Michael Best & Friedrich LLP
- Priority: JP2015-146670 20150724
- International Application: PCT/JP2016/063222 WO 20160427
- International Announcement: WO2017/018013 WO 20170202
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G06F12/00

Abstract:
Delay overhead in a memory device is eliminated.A command accepting unit accepts a read command requesting data reading from the memory device. A control unit selects, in accordance with a state of the memory device, one of a first mode in which a read request, requesting data reading from a memory cell array of the memory device and output of the read data, is issued to the memory device after completion of a preceding request and a second mode in which a sense request requesting data reading from the memory cell array is issued and then a data-out request requesting output of the data read by the sense request is issued to the memory device after a lapse of predetermined time from completion of the preceding request. A request issuing unit issues a request to the memory device in accordance with the first or the second mode selected by the control unit.
Public/Granted literature
- US20180174652A1 MEMORY CONTROLLER, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM Public/Granted day:2018-06-21
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