Invention Grant
- Patent Title: Semiconductor structure and method of forming
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Application No.: US16042220Application Date: 2018-07-23
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Publication No.: US10177105B2Publication Date: 2019-01-08
- Inventor: Chen-Hua Yu , Yu-Hsiang Hu , Hung-Jui Kuo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/29
- IPC: H01L23/29 ; H01L23/31 ; H01L25/00 ; H01L23/522 ; H01L23/528 ; H01L25/065 ; H01L21/56 ; H01L23/00

Abstract:
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
Public/Granted literature
- US20180350763A1 Semiconductor Structure and Method of Forming Public/Granted day:2018-12-06
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