Invention Grant
- Patent Title: PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications
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Application No.: US15354808Application Date: 2016-11-17
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Publication No.: US10171089B2Publication Date: 2019-01-01
- Inventor: Feng Wei Kuo , Chewn-Pu Jou , Lan-Chou Cho , Huan-Neng Chen , Robert Bogdan Staszewski , Seyednaser Pourmousavian
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L1/00 ; H03L7/099 ; H03K5/151 ; H03L7/091
Abstract:
An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.
Public/Granted literature
- US20180138911A1 PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS Public/Granted day:2018-05-17
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