Invention Grant
- Patent Title: Manufacturing method of semiconductor device and semiconductor device
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Application No.: US15607692Application Date: 2017-05-30
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Publication No.: US10170564B2Publication Date: 2019-01-01
- Inventor: Katsunori Ueno , Shinya Takashima
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kanagawa
- Priority: JP2016-136796 20160711
- Main IPC: H01L31/0336
- IPC: H01L31/0336 ; H01L29/207 ; H01L29/20 ; H01L29/423 ; H01L29/66 ; H01L29/78

Abstract:
Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
Public/Granted literature
- US20180012964A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Public/Granted day:2018-01-11
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