Invention Grant
- Patent Title: Reduction of dishing during chemical mechanical polish of gate structure
-
Application No.: US15489875Application Date: 2017-04-18
-
Publication No.: US10170334B2Publication Date: 2019-01-01
- Inventor: Ta-Wei Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L21/321
- IPC: H01L21/321 ; H01L21/8234 ; H01L27/088 ; H01L29/66 ; H01L29/40

Abstract:
A semiconductor device includes a semiconductor substrate, a gate structure and at least one CMP resistant structure. The gate structure is over the semiconductor substrate. The CMP resistant structure is embedded in a top surface of the gate structure. The CMP resistant structure has a CMP resistance property different from a CMP resistance property of the gate structure.
Public/Granted literature
- US20180301348A1 REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE Public/Granted day:2018-10-18
Information query
IPC分类: