Invention Grant
- Patent Title: Method of double patterning lithography process using plurality of mandrels for integrated circuit applications
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Application No.: US15489037Application Date: 2017-04-17
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Publication No.: US10170306B2Publication Date: 2019-01-01
- Inventor: Chung-Ju Lee , Hsin-Chieh Yao , Shau-Lin Shue , Tien-I Bao , Yung-Hsu Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L21/033 ; H01L21/768 ; H01L21/311

Abstract:
A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.
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