Invention Grant
- Patent Title: Apparatuses and methods using negative voltages in part of memory write read, and erase operations
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Application No.: US13437547Application Date: 2012-04-02
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Publication No.: US10170187B2Publication Date: 2019-01-01
- Inventor: Koji Sakui
- Applicant: Koji Sakui
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/34

Abstract:
Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described.
Public/Granted literature
- US20130258785A1 APPARATUSES AND METHODS INCLUDING MEMORY WRITE, READ, AND ERASE OPERATIONS Public/Granted day:2013-10-03
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