A memory device includes: a cell array connected to a plurality of word lines and bit lines, the cell array including a plurality of memory cells each including a variable resistance element and a bidirectional selection element; a selection circuit that selects a selected word line and a selected bit line; and control logic that controls the selection circuit such that in a stand-by state, wherein the word lines and the bit lines which are connected to memory cells of a first area of the cell array are maintained in a discharge state, and the word lines and bit lines which are connected to memory cells of a second area of the cell array are maintained in a precharge state.