Invention Grant
- Patent Title: Low-power clocking for a high-speed memory interface
-
Application No.: US15204755Application Date: 2016-07-07
-
Publication No.: US10169262B2Publication Date: 2019-01-01
- Inventor: David West , Vaishnav Srinivas , Michael Brunolli , Jungwon Suh
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/16 ; G06F13/40 ; G11C7/22 ; H03L7/08

Abstract:
Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.
Public/Granted literature
- US20170017587A1 LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE Public/Granted day:2017-01-19
Information query