Invention Grant
- Patent Title: Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
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Application No.: US15531979Application Date: 2015-11-05
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Publication No.: US10096772B2Publication Date: 2018-10-09
- Inventor: Jun Okuno
- Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sheridan Ross P.C.
- International Application: PCT/JP2015/005552 WO 20151105
- International Announcement: WO2016/092741 WO 20160616
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24 ; H01L27/10
Abstract:
Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
Public/Granted literature
- US20170338410A1 METHODS FOR FABRICATING A MEMORY DEVICE WITH AN ENLARGED SPACE BETWEEN NEIGHBORING BOTTOM ELECTRODES Public/Granted day:2017-11-23
Information query
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