Invention Grant
- Patent Title: Interconnect structure for stacked device
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Application No.: US13937055Application Date: 2013-07-08
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Publication No.: US10096515B2Publication Date: 2018-10-09
- Inventor: Shu-Ting Tsai , Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Chih-Hui Huang , Sheng-Chau Chen , Shih-Pei Chou , Chia-Chieh Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/31 ; H01L23/528 ; H01L23/538 ; H01L21/768 ; H01L23/00 ; H01L25/00 ; H01L25/065

Abstract:
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
Public/Granted literature
- US20140264929A1 Interconnect Structure for Stacked Device Public/Granted day:2014-09-18
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