Invention Grant
- Patent Title: Semiconductor memory device in which an array chip including three-dimensionally disposed memory cells bonded to a control circuit chip
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Application No.: US15388318Application Date: 2016-12-22
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Publication No.: US10090315B2Publication Date: 2018-10-02
- Inventor: Yoshiaki Fukuzumi , Hideaki Aochi
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2014-186684 20140912
- Main IPC: H01L27/11563
- IPC: H01L27/11563 ; H01L27/11575 ; H01L27/11568 ; H01L27/11573 ; H01L27/11582 ; H01L21/768
Abstract:
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
Public/Granted literature
- US20170103994A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME Public/Granted day:2017-04-13
Information query
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