Invention Grant
- Patent Title: Method of speeding up output alignment in a digital phase locked loop
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Application No.: US15597726Application Date: 2017-05-17
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Publication No.: US10069503B2Publication Date: 2018-09-04
- Inventor: Changhui Cathy Zhang , Qu Gary Jin , Mark A. Warriner , Kamran Rahbar
- Applicant: Microsemi Semiconductor ULC
- Applicant Address: CA Kanata, Ontario
- Assignee: Microsemi Semiconductor ULC
- Current Assignee: Microsemi Semiconductor ULC
- Current Assignee Address: CA Kanata, Ontario
- Agent Simon Kahn
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/10 ; H03L7/18 ; H03K5/135 ; H03L7/099 ; H03L7/091 ; H03K5/00

Abstract:
To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.
Public/Granted literature
- US20170346494A1 METHOD OF SPEEDING UP OUTPUT ALIGNMENT IN A DIGITAL PHASE LOCKED LOOP Public/Granted day:2017-11-30
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