Invention Grant
- Patent Title: Shallow trench isolation area having buried capacitor
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Application No.: US15365237Application Date: 2016-11-30
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Publication No.: US10068897B2Publication Date: 2018-09-04
- Inventor: Hartmud Terletzki
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L27/02 ; H01L49/02 ; H01L29/66 ; H01L29/94 ; H01L21/762 ; H01L21/8234 ; H01L29/06

Abstract:
A method of forming a semiconductor device includes providing a semiconductor substrate including a source/drain region, an active transistor region, and a substrate contact region coupled to a body region. A shallow trench isolation (STI) area is formed in a major surface of the semiconductor substrate in between the active transistor region and the substrate contact region. The method further includes at least partially burying at least one capacitor in the STI area.
Public/Granted literature
- US20170084607A1 Shallow Trench Isolation Area Having Buried Capacitor Public/Granted day:2017-03-23
Information query
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