Invention Grant
- Patent Title: Method of forming spacers for a gate of a transistor
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Application No.: US15267624Application Date: 2016-09-16
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Publication No.: US10043890B2Publication Date: 2018-08-07
- Inventor: Olivier Pollet , Nicolas Posseme
- Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1558845 20150918
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/265 ; H01L21/3065 ; H01L21/308 ; H01L21/324 ; H01L21/8234 ; H01L21/8238 ; H01L21/311 ; H01L21/3115

Abstract:
A method is provided for forming spacers of a gate of a field effect transistor, the gate including flanks and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer covering the gate; after the step of forming, at least one step of modifying the dielectric layer by putting the dielectric layer into presence of a plasma creating a bombarding of light ions; and at least one step of removing the modified dielectric layer including a dry etching performed by putting the modified dielectric layer into presence of a gaseous mixture including at least one first component with a hydrofluoric acid base that transforms the modified dielectric layer into non-volatile residue, and removing the non-volatile residue via a wet clean performed after the dry etching or a thermal annealing of sublimation performed after or during the dry etching.
Public/Granted literature
- US20170084720A1 METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR Public/Granted day:2017-03-23
Information query
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