Invention Grant
- Patent Title: Through silicon vias for backside connection
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Application No.: US14675671Application Date: 2015-03-31
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Publication No.: US10042488B2Publication Date: 2018-08-07
- Inventor: Stephen L. Morein , Joseph Kurth Reynolds
- Applicant: Synaptics Incorporated
- Applicant Address: US CA San Jose
- Assignee: SYNAPTICS INCORPORATED
- Current Assignee: SYNAPTICS INCORPORATED
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L27/14
- IPC: H01L27/14 ; G06F3/044 ; H01L21/768 ; H01L23/48

Abstract:
In an example, a method of processing an integrated circuit (IC) die including active circuitry formed on a substrate and a front side having a plurality of metal layers formed on the substrate. The method includes forming vias in a substrate of the IC die using a laser configured to drill the vias from the front side of the IC die. The method includes forming metal contacts on first metal pads, and metal interconnects between second metal pads and the vias, using an single electroplating process, where the first metal pads and the second metal pads are exposed parts of a top layer of the plurality of metal layers, and where the metal interconnects at least partially fill the vias. The method includes thinning the substrate of the IC die to expose the metal interconnects in the vias at a back side of the IC die opposite the front side.
Public/Granted literature
- US20150286318A1 THROUGH SILICON VIAS FOR BACKSIDE CONNECTION Public/Granted day:2015-10-08
Information query
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