Through silicon vias for backside connection
Abstract:
In an example, a method of processing an integrated circuit (IC) die including active circuitry formed on a substrate and a front side having a plurality of metal layers formed on the substrate. The method includes forming vias in a substrate of the IC die using a laser configured to drill the vias from the front side of the IC die. The method includes forming metal contacts on first metal pads, and metal interconnects between second metal pads and the vias, using an single electroplating process, where the first metal pads and the second metal pads are exposed parts of a top layer of the plurality of metal layers, and where the metal interconnects at least partially fill the vias. The method includes thinning the substrate of the IC die to expose the metal interconnects in the vias at a back side of the IC die opposite the front side.
Public/Granted literature
Information query
Patent Agency Ranking
0/0