Invention Grant
- Patent Title: Decoupling arrangement
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Application No.: US14945762Application Date: 2015-11-19
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Publication No.: US10015878B2Publication Date: 2018-07-03
- Inventor: William L. Barber , Keith Pinson , Andrew P. Collins , Boping Wu , Isaac Ali , Colin L. Perry
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H02H9/04
- IPC: H02H9/04 ; H05K1/02 ; H01L23/50

Abstract:
In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.
Public/Granted literature
- US20160309580A1 DECOUPLING ARRANGEMENT Public/Granted day:2016-10-20
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