A clock detector a first delay circuit delaying an input clock by a first delay time and outputting the delayed input clock as a delayed clock signal, an edge detection circuit receiving the input clock and the delayed clock signal to generate an output signal including pulses which are created in synchronization with edges of the input clock, a delay/inversion circuit delaying the output signal of the edge detection circuit by a second delay time and inverting the delayed output signal to output the inverted signal as an output signal, a first flip-flop receiving the input clock to generate a first output signal, a second flip-flop receiving the first output signal to generate a second output signal, and a clock detection signal generation circuit receiving the first and second output signals to generate a clock detection signal.