Invention Grant
- Patent Title: Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and method of manufacturing the same
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Application No.: US15399064Application Date: 2017-01-05
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Publication No.: US10014372B1Publication Date: 2018-07-03
- Inventor: Effendi Leobandung
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L21/8234 ; H01L29/08 ; H01L29/10 ; H01L29/20 ; H01L27/088 ; H01L29/78 ; H01L29/66 ; H01L21/02 ; H01L21/3213 ; H01L21/225

Abstract:
After providing a Group IV semiconductor nanowire on a substrate, a sacrificial material portion is formed on sidewalls of a bottom portion of the Group IV semiconductor nanowire. A sacrificial gate layer is then formed over the sacrificial material portion to laterally surround a middle portion of the Group IV semiconductor nanowire, followed by forming a sacrificial spacer on sidewalls of a remaining top portion of the Group IV semiconductor nanowire. After replacing the Group IV semiconductor nanowire with a Group III-V compound semiconductor nanowire, the sacrificial material portion, sacrificial spacer and sacrificial gate layer are replaced by a first epitaxial semiconductor region which serves as a bottom source/drain region, a second epitaxial semiconductor region which serves as a top source/drain region, and a functional gate structure, respectively.
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