- Patent Title: Semiconductor integrated circuit device having enhancement type NMOS and depression type MOS with N-type channel impurity region and P-type impurity layer under N-type channel impurity region
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Application No.: US15247144Application Date: 2016-08-25
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Publication No.: US10014294B2Publication Date: 2018-07-03
- Inventor: Hirofumi Harada , Masayuki Hashitani
- Applicant: SII Semiconductor Corporation
- Applicant Address: JP
- Assignee: ABLIC Inc.
- Current Assignee: ABLIC Inc.
- Current Assignee Address: JP
- Agency: Adams & Wilks
- Priority: JP2012-215034 20120927
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L27/092 ; H01L29/06 ; H01L29/78
Abstract:
Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.
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