Invention Grant
- Patent Title: Method of wafer dicing for backside metallization
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Application No.: US15182224Application Date: 2016-06-14
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Publication No.: US10014262B2Publication Date: 2018-07-03
- Inventor: L. Scott Klingbeil , Colby Rampley
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/683 ; H01L21/78

Abstract:
Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.
Public/Granted literature
- US20170358537A1 METHOD OF WAFER DICING FOR BACKSIDE METALLIZATION Public/Granted day:2017-12-14
Information query
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