Invention Grant
- Patent Title: Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors
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Application No.: US15201122Application Date: 2016-07-01
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Publication No.: US10014252B2Publication Date: 2018-07-03
- Inventor: Shih-Cheng Chang , Liang-Chen Lin , Fu-Tsai Hou , Tung-Chin Yeh , Shih-Kai Lin , Gia-Her Lu , Jyun-Lin Wu , Hsien-Pin Hu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/525
- IPC: H01L23/525 ; H01L23/522 ; H01L23/532 ; H01L23/528

Abstract:
An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
Public/Granted literature
- US20160315050A1 CAPACITOR WITH FUSE PROTECTION Public/Granted day:2016-10-27
Information query
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