Invention Grant
- Patent Title: Method of singulating semiconductor wafer having a plurality of die and a back layer disposed along a major surface
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Application No.: US15384646Application Date: 2016-12-20
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Publication No.: US10014217B2Publication Date: 2018-07-03
- Inventor: Gordon M. Grivna
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agent Kevin B. Jackson
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/3065 ; H01L21/67 ; H01L21/683 ; H01L23/544
Abstract:
De are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.
Public/Granted literature
- US20170103922A1 METHOD OF SINGULATING SEMICONDUCTOR WAFER HAVING BACK LAYER Public/Granted day:2017-04-13
Information query
IPC分类:
