Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US15382646Application Date: 2016-12-17
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Publication No.: US10014067B2Publication Date: 2018-07-03
- Inventor: Keiichi Maekawa , Shiro Kamohara , Yasushi Yamagata , Yoshiki Yamamoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2016-044528 20160308
- Main IPC: G11C17/16
- IPC: G11C17/16 ; G11C17/18 ; H01L21/266 ; H01L21/283 ; H01L21/768 ; H01L21/84 ; H01L27/12 ; H01L29/36

Abstract:
To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.
Public/Granted literature
- US20170263328A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2017-09-14
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